FreeEMS  0.2.0-SNAPSHOT-282-g9efc524
9S12XDP512.h
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1 /* FreeEMS - the open source engine management system
2  *
3  * Copyright 2008-2013 Fred Cooke
4  *
5  * This file is part of the FreeEMS project.
6  *
7  * FreeEMS software is free software: you can redistribute it and/or modify
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25 
26 
27 /** @file
28  *
29  * @ingroup allHeaders
30  * @ingroup globalHeaders
31  *
32  * @brief MC9S12XDP512 register definitions
33  *
34  * This is the device header for the FreeScale MC9S12XDP512 MCU. It contains
35  * declarations that allow access to all of the devices control registers.
36  *
37  * These are the full basic register definitions for the Freescale 9S12XDP512
38  * processor as taken from MC9S12XDP512V2.pdf Appendix G
39  */
40 
41 
42 /* see if we've seen this, if not, mark seen and process */
43 #ifndef FILE_9S12XDP512_H_SEEN
44 #define FILE_9S12XDP512_H_SEEN
45 
46 
47 /* shortcuts to speed formatting */
48 /* www.atmel.com/dyn/resources/prod_documents/avr_3_04.pdf First page, second column */
49 /* http://www.ee.nmt.edu/~rison/ee308_spr06/homepage.html */
50 /* extra parentheses for clarity and guarantee of precedence */
51 
52 /* Dereferenced Volatile Unsigned Char Pointer */
53 #define DVUCP(address) (*((volatile unsigned char*)(address)))
54 /* Dereferenced Volatile Unsigned Short Pointer */
55 #define DVUSP(address) (*((volatile unsigned short*)(address)))
56 
57 /* Address Volatile Unsigned Char Pointer */
58 #define AVUCP(address) ((volatile unsigned char*)(address))
59 /* Address Volatile Unsigned Short Pointer */
60 #define AVUSP(address) ((volatile unsigned short*)(address))
61 
62 
63 
64 /* Port Integration Module - Reordered within sections for clarity */
65 /* PIM information from 5 tables the last of which is spread over three pages */
66 
67 /* Plain ports output switch, input state registers */
68 #define PORTS_BA DVUSP(0x0001) /// @todo TODO is this address wrong? Test this... /* Both A and B combined as a 16 bit register for ignition access */
69 #define PORTA DVUCP(0x0000)
70 #define PORTB DVUCP(0x0001)
71 #define PORTE DVUCP(0x0008)
72 #define PORTK DVUCP(0x0032)
73 #define PORTC DVUCP(0x0004) // These pins are not bonded on the 112 pin package
74 #define PORTD DVUCP(0x0005) // These pins are not bonded on the 112 pin package
75 
76 
77 /* Plain ports Data Direction Registers */
78 #define DDRA DVUCP(0x0002)
79 #define DDRB DVUCP(0x0003)
80 #define DDRE DVUCP(0x0009)
81 #define DDRK DVUCP(0x0033)
82 
83 
84 #define DDRC DVUCP(0x0006) /* these pins are not bonded on the 112 pin package but need switching to output */
85 #define DDRD DVUCP(0x0007) /* these pins are not bonded on the 112 pin package but need switching to output */
86 
87 
88 /* 0b1//1//00 */
89 /* --K//E//BA */
90 /* TODO NOTE: the sixth bit controls pull up on BKGD and VREGEN pins set this to ???? */
91 /* NOTE: pull up on port E is for 0-4 and 7, ports 5 and 6 are pulled down during reset and never pulled up. */
92 #define PUCR DVUCP(0x000C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
93 
94 
95 /* 0b1//0//00 */
96 /* --K//E//BA */
97 /* NOTE: reduced drive affects all pins of all ports listed above. */
98 #define RDRIV DVUCP(0x000D) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
99 
100 
101 #define ECLKCTL DVUCP(0x001C) /* Comes up 0b_1100_0000 = both pins off in normal single chip mode */
102 #define IRQCR DVUCP(0x001E) /* 0 in bit 7 makes it ultra sensitive, 1 makes it falling edge sensitive. 0 in bit 6 turns interrupts off, 1 in bit 6 turns them on. */
103 
104 
105 /* Port T registers */
106 #define PTT DVUCP(0x0240) /* GPIO output register, can not be read from reliably, use PTIT instead */
107 #define PORTT DVUCP(0x0240) /* Duplicate definition for consistency */
108 #define PTIT DVUCP(0x0241) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
109 #define DDRT DVUCP(0x0242) /* TODO configure all IO as outputs until we need it */
110 #define RDRT DVUCP(0x0243) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
111 #define PERT DVUCP(0x0244) /* pull up/down enable when used as an input, 0 = no pull up, 1 = pull up on */
112 #define PPST DVUCP(0x0245) /* 0 = pull up, 1 = pull down */
113 
114 
115 /* Port S registers */
116 #define PTS DVUCP(0x0248)
117 #define PORTS DVUCP(0x0248) /* Duplicate definition for consistency */
118 #define PTIS DVUCP(0x0249) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
119 #define DDRS DVUCP(0x024A) /* TODO configure all IO as outputs until we need it */
120 #define RDRS DVUCP(0x024B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
121 #define PERS DVUCP(0x024C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
122 #define PPSS DVUCP(0x024D) /* 0 = pull up, 1 = pull down */
123 #define WOMS DVUCP(0x024E) /* wired OR mode TODO find out what this actually means in real terms. */
124 
125 
126 /* Port M registers */
127 #define PTM DVUCP(0x0250)
128 #define PORTM DVUCP(0x0250) /* Duplicate definition for consistency */
129 #define PTIM DVUCP(0x0251) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
130 #define DDRM DVUCP(0x0252) /* TODO configure all IO as outputs until we need it */
131 #define RDRM DVUCP(0x0253) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
132 #define PERM DVUCP(0x0254) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
133 #define PPSM DVUCP(0x0255) /* 0 = pull up, 1 = pull down */
134 #define WOMM DVUCP(0x0256) /* wired OR mode TODO find out what this actually means in real terms. */
135 
136 
137 /* this should be set to the following bit mask xx????00 */
138 #define MODRR DVUCP(0x0257)
139 
140 
141 /* Port P registers */
142 #define PTP DVUCP(0x0258)
143 #define PORTP DVUCP(0x0258) /* Duplicate definition for consistency */
144 #define PTIP DVUCP(0x0259) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
145 #define DDRP DVUCP(0x025A) /* TODO configure all IO as outputs until we need it */
146 #define RDRP DVUCP(0x025B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
147 #define PERP DVUCP(0x025C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
148 #define PPSP DVUCP(0x025D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
149 #define PIEP DVUCP(0x025E) /* interrupt enable, turns on interrupts */
150 #define PIFP DVUCP(0x025F) /* interrupt flag, write a 1 to clear it */
151 
152 
153 /* Port H registers */
154 #define PTH DVUCP(0x0260)
155 #define PORTH DVUCP(0x0260) /* Duplicate definition for consistency */
156 #define PTIH DVUCP(0x0261) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
157 #define DDRH DVUCP(0x0262) /* TODO configure all IO as outputs until we need it */
158 #define RDRH DVUCP(0x0263) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
159 #define PERH DVUCP(0x0264) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
160 #define PPSH DVUCP(0x0265) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
161 #define PIEH DVUCP(0x0266) /* interrupt enable, turns on interrupts */
162 #define PIFH DVUCP(0x0267) /* interrupt flag, write a 1 to clear it */
163 
164 
165 /* Port J registers */
166 #define PTJ DVUCP(0x0268)
167 #define PORTJ DVUCP(0x0268) /* Duplicate definition for consistency */
168 #define PTIJ DVUCP(0x0269) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
169 #define DDRJ DVUCP(0x026A) /* TODO configure all IO as outputs until we need it */
170 #define RDRJ DVUCP(0x026B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
171 #define PERJ DVUCP(0x026C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
172 #define PPSJ DVUCP(0x026D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
173 #define PIEJ DVUCP(0x026E) /* interrupt enable, turns on interrupts */
174 #define PIFJ DVUCP(0x026F) /* interrupt flag, write a 1 to clear it */
175 
176 
177 /* #define ATD0PT1 DVUCP(0x0271) we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */
178 /* #define ATD0DDR1 DVUCP(0x0273) for use as an input, ATD0DIEN has to be set to 1. for use as an output? */
179 /* #define ATD0RDR1 DVUCP(0x0275) reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
180 #define ATD0PER1 DVUCP(0x0277) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
181 
182 /* #define ATD1PT1 DVUCP(0x0279) we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */
183 /* #define ATD1DDR1 DVUCP(0x027B) for use as an input, ATD1DIEN1 has to be set to 1. for use as an output? */
184 /* #define ATD1RDR1 DVUCP(0x027D) reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
185 /* #define ATD1PER1 DVUCP(0x027F) pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
186 
187 /* Not available on 112 pin version */
188 /* #define ATD1DDR0 DVUCP(0x027A) */
189 /* 0x0278 #define ATD1PT0 DVUCP() */
190 /* 0x027C #define ATD1RDR0 DVUCP() */
191 /* 0x027E #define ATD1PER0 DVUCP() */
192 
193 
194 /* Memory Mapping Control registers TODO configure these to suit our application. */
195 /* MMC 1/4 */
196 //0x000B MODE DVUCP()
197 //0x000A MMCCTL0 DVUCP()
198 //0x0013 MMCCTL1 DVUCP()
199 
200 
201 /* Page control registers */
202 #define RPAGE DVUCP(0x0016) /* Used to page table data in and out of visible memory. */
203 //0x0017 EPAGE DVUCP() /* /* TODO similar to above if we need another 2k of eeprom. what are advantages/disadvantages of eeprom over flash?? */
204 #define PPAGE DVUCP(0x0030) /* TODO look at the best way to use the flash space in a complete system with a lot of code and data. used by compiler and maybe us to switch flash pages for loading/unloading data. */
205 //0x0010 GPAGE DVUCP() /* /* Global page register for global instruction addressing. I doubt we will use this. */
206 //0x0011 DIRECT DVUCP() /* /* Direct addressing mode control register. I doubt we will use this. */
207 
208 
209 // MMC 4/4
210 #define RAMWPC DVUCP(0x011C) /* RAM Write Protection register, the pdf document appears to be incorrect for this, best not to touch it. */
211 #define RAMXGU DVUCP(0x011D) /* XGATE Upper region limit, this defines how much RAM we give the xgate to work with. */
212 #define RAMSHL DVUCP(0x011E) /* Shared memory lower boundary register, this defines the lower limit of the overlap between XGATE RAM and CPU RAM */
213 #define RAMSHU DVUCP(0x011F) /* Shared memory upper boundary register, this defines the upper limit of the overlap between XGATE RAM and CPU RAM */
214 
215 
216 //// EBI
217 //0x000E EBICTL0 DVUCP() /*
218 //0x000F EBICTL1 DVUCP() /*
219 
220 
221 //// Misc Peripheral
222 //0x001A PARTIDH DVUCP() /*
223 //0x001B PARTIDL DVUCP() /*
224 
225 
226 /* Clock and Reset Generator */
227 #define SYNR DVUCP(0x0034) /* Multiplier of result of division by REFDV below, output is new PLL/Bus freqency. */
228 #define REFDV DVUCP(0x0035) /* Divisor of external clock frequency pre being multiplied by SYNR above. */
229 //0x0036 CTFLG DVUCP() /*
230 #define CRGFLG DVUCP(0x0037) /* Clock and Reset Generator flags, we use this to determine when the PLL is stable and ready to use. Also to reset the RTI flag. */
231 #define CRGINT DVUCP(0x0038) /* Bit 7 is RTIE RTI enable bit. */
232 #define CLKSEL DVUCP(0x0039) /* Clock select register, choose PLL or external clock with this. */
233 #define PLLCTL DVUCP(0x003A) /* PLL frequency generator control register, used for setting the bus frequency. */
234 #define RTICTL DVUCP(0x003B) /* Divider select register */
235 #define COPCTL DVUCP(0x003C) /* COP watch dog control register */
236 //0x003D FORBYP DVUCP() /*
237 #define ARMCOP DVUCP(0x003F) /* Computer operating properly timer, we won't be using this at least until we have profiled the running application. it will just cause headaches otherwise. */
238 
239 
240 /* Enhanced Capture Timer */
241 /* see reference document from Huang course overview/notes : http://www.ee.nmt.edu/~rison/ee308_spr06/lectures.html */
242 /* see this link for a discussion of the old 68hc12 timer http://www.seattlerobotics.org/encoder/nov97/68hc12.html */
243 
244 #define TCNT DVUSP(0x0044) /* Timer counter 16 bit (0x0044 TCNT (hi), 0x0045 TCNT (lo)) */
245 
246 /* Behavioural control registers (dual purpose) */
247 #define TIOS DVUCP(0x0040) /* Selects input capture or output compare mode for each timer pin */
248 #define TIE DVUCP(0x004C) /* Timer channel interrupt enable register */
249 #define TSCR1 DVUCP(0x0046) /* Timer System Control Register 1 */
250 #define TSCR2 DVUCP(0x004D) /* Timer System Control Register 2 */
251 #define TFLG DVUCP(0x004E) /* Timer channel flags */
252 #define TFLGOF DVUCP(0x004F) /* Timer over flow flag */
253 #define PTPSR DVUCP(0x006E) /* Precision prescaler for the main timer */
254 
255 /* Output compare control registers */
256 #define TTOV DVUCP(0x0047) /* Timer Toggle on Overflow output compare control */
257 #define CFORC DVUCP(0x0041) /* Output compare force, write a 1 to make the programmed action occur now */
258 #define OC7M DVUCP(0x0042) /* Channel 7 output compare other pins control mask */
259 #define OC7D DVUCP(0x0043) /* Channel 7 output compare other pins states */
260 
261 /* Timer output compare action control registers
262  * OMx OLx Action
263  * 0 0 Timer disconnected from output pin logic
264  * 0 1 Toggle OCx output line
265  * 1 0 Clear OCx output line to zero
266  * 1 1 Set OCx output line to one */
267 #define TCTL1 DVUCP(0x0048) /* (M,L) 77,66,55,44 */
268 #define TCTL2 DVUCP(0x0049) /* (M,L) 33,22,11,00 */
269 #define TCTL1_ADDR AVUCP(0x0048) /* (M,L) 77,66,55,44 */
270 #define TCTL2_ADDR AVUCP(0x0049) /* (M,L) 33,22,11,00 */
271 
272 
273 /* Input capture control registers */
274 #define DLYCT DVUCP(0x0069) /* Delay counter control register (minimum tooth width) */
275 #define ICSYS DVUCP(0x006B) /* Input capture behaviour control register */
276 #define ICOVW DVUCP(0x006A) /* Input capture overwrite allow */
277 
278 /* Timer input capture edge detection control registers
279  * EDGxB EDGxA Configuration
280  * 0 0 Capture disabled
281  * 0 1 Capture on rising edges only
282  * 1 0 Capture on falling edges only
283  * 1 1 Capture on any edge (rising or falling) */
284 #define TCTL3 DVUCP(0x004A) /* (B,A) 77,66,55,44 */
285 #define TCTL4 DVUCP(0x004B) /* (B,A) 33,22,11,00 */
286 
287 /* Input capture holding registers for 0 - 3 */
288 #define TC0H DVUSP(0x0078) /* 16 bit (0x0078 TC0H (hi), 0x0079 TC0H (lo)) */
289 #define TC1H DVUSP(0x007A) /* 16 bit (0x007A TC1H (hi), 0x007B TC1H (lo)) */
290 #define TC2H DVUSP(0x007C) /* 16 bit (0x007C TC2H (hi), 0x007D TC2H (lo)) */
291 #define TC3H DVUSP(0x007E) /* 16 bit (0x007E TC3H (hi), 0x007F TC3H (lo)) */
292 
293 /* Time value comparison/storage registers for each timer channel */
294 #define TC0 DVUSP(0x0050) /* 16 bit (0x0050 TC0 (hi), 0x0051 TC0 (lo)) */
295 #define TC1 DVUSP(0x0052) /* 16 bit (0x0052 TC1 (hi), 0x0053 TC1 (lo)) */
296 #define TC2 DVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */
297 #define TC3 DVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */
298 #define TC4 DVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */
299 #define TC5 DVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */
300 #define TC6 DVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */
301 #define TC7 DVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */
302 
303 #define TC2_ADDR AVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */
304 #define TC3_ADDR AVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */
305 #define TC4_ADDR AVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */
306 #define TC5_ADDR AVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */
307 #define TC6_ADDR AVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */
308 #define TC7_ADDR AVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */
309 
310 
311 
312 /* Pulse accumulator control registers */
313 #define ICPAR DVUCP(0x0068)
314 // Bits for PACTL
315 // 7 6 5 4 3 2 1 0
316 // RESERVED PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
317 #define PACTL DVUCP(0x0060)
318 #define PAFLG DVUCP(0x0061)
319 #define PBCTL DVUCP(0x0070)
320 #define PBFLG DVUCP(0x0071)
321 /* Pulse accumulator count registers dual access, 8 or 16 bit */
322 #define PACNUS2 DVUSP(0x0062) /* 16 bit (0x0062 PACN3, 0x0063 PACN2) */
323 #define PACNUS0 DVUSP(0x0064) /* 16 bit (0x0064 PACN1, 0x0065 PACN0) */
324 #define PACN3 DVUCP(0x0062) /* high */
325 #define PACN2 DVUCP(0x0063) /* low */
326 #define PACN1 DVUCP(0x0064) /* high */
327 #define PACN0 DVUCP(0x0065) /* low */
328 /* Pulse accumulator holding registers dual access, 8 or 16 bit */
329 #define PACHUS2 DVUSP(0x0072) /* 16 bit (0x0072 PACH3, 0x0073 PACH2) */
330 #define PACHUS0 DVUSP(0x0074) /* 16 bit (0x0074 PACH1, 0x0075 PACH0) */
331 #define PA3H DVUCP(0x0072) /* high */
332 #define PA2H DVUCP(0x0073) /* low */
333 #define PA1H DVUCP(0x0074) /* high */
334 #define PA0H DVUCP(0x0075) /* low */
335 
336 
337 /* Modulus down counter control registers */
338 #define MCCTL DVUCP(0x0066) /* Modulus control register */
339 #define MCFLG DVUCP(0x0067) /* Modulus flag (high bit) and input edge indicators (low 4 bits) */
340 #define MCCNT DVUSP(0x0076) /* 16 bit (0x0076 MCCNT (hi), 0x0077 MCCNT (lo)) */
341 #define PTMCPSR DVUCP(0x006F) /* Precision prescaler for the modulus down counter */
342 
343 
344 /* Analog To Digital converter 1 */
345 /* TODO Configure these and disable the non functional 16 - 23 144 pin section! */
346 #define ATD1CTL0 DVUCP(0x0080) /* 0 - 3 define which ADC channel to wrap on when doing multiple channels */
347 #define ATD1CTL1 DVUCP(0x0081) /* External trigger select when enabled in other control register */
348 #define ATD1CTL2 DVUCP(0x0082) /* bit 7 turns the ADC block on. */
349 #define ATD1CTL3 DVUCP(0x0083) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */
350 #define ATD1CTL4 DVUCP(0x0084) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */
351 #define ATD1CTL5 DVUCP(0x0085) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */
352 //0x0086 ATD1STAT0 DVUCP() /*
353 //0x0088 ATD1TEST0 DVUCP() /*
354 //0x0089 ATD1TEST1 DVUCP() /*
355 //0x008A ATD1STAT2 DVUCP() /*
356 //0x008B ATD1STAT1 DVUCP() /*
357 #define ATD1DIEN0 DVUCP(0x008C) /* Digital input enable - these pins are not bonded on the 112 pin package */
358 #define ATD1DIEN1 DVUCP(0x008D) /* Digital input enable */
359 //0x008E ATD1PTAD0 DVUCP() /* digital use only */
360 //0x008F ATD1PTAD1 DVUCP() /* digital use only */
361 // one short for each hi lo par based on hi address. label with WORD for consistency
362 #define ATD1_BASE 0x0090
363 #define ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ /* SpareADC (NC) */
364 #define ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ /* SpareADC (NC) */
365 #define ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ /* SpareADC (NC) */
366 #define ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ /* SpareADC (NC) */
367 #define ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ /* SpareADC (NC) */
368 #define ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ /* SpareADC (NC) */
369 #define ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ /* SpareADC (NC) */
370 #define ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ /* SpareADC (NC) */
371 
372 
373 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */
374 //0x00A0 ATD1DR8H
375 //0x00A1 ATD1DR8L
376 //0x00A2 ATD1DR9H
377 //0x00A3 ATD1DR9L
378 //0x00A4 ATD1DR10H
379 //0x00A5 ATD1DR10L
380 //0x00A6 ATD1DR11H
381 //0x00A7 ATD1DR11L
382 //0x00A8 ATD1DR12H
383 //0x00A9 ATD1DR12L
384 //0x00AA ATD1DR13H
385 //0x00AB ATD1DR13L
386 //0x00AC ATD1DR14H
387 //0x00AD ATD1DR14L
388 //0x00AE ATD1DR15H
389 //0x00AF ATD1DR15L
390 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */
391 
392 
393 /* IIC1 - Inter Intergrated Circuit interface 1 TODO configure and use */
394 //0x00B0 IBAD DVUCP() /*
395 //0x00B1 IBFD DVUCP() /*
396 //0x00B2 IBCR DVUCP() /*
397 //0x00B3 IBSR DVUCP() /*
398 //0x00B4 IBDR DVUCP() /*
399 
400 
401 /* SCI2 */
402 //0x00B8 SCI2BDH
403 //0x00B8 SCI2ASR1
404 //0x00B9 SCI2BDL
405 //0x00B9 SCI2ACR1
406 //0x00BA SCI2CR1
407 //0x00BA SCI2ACR2
408 //0x00BB SCI2CR2
409 //0x00BC SCI2SR1
410 //0x00BD SCI2SR2
411 //0x00BE SCI2DRH
412 //0x00BF SCI2DRL
413 
414 
415 /* SCI3 */
416 //0x00C0 SCI3BDH
417 //0x00C0 SCI3ASR1
418 //0x00C1 SCI3BDL
419 //0x00C1 SCI3ACR1
420 //0x00C2 SCI3CR1
421 //0x00C2 SCI3ACR2
422 //0x00C3 SCI3CR2
423 //0x00C4 SCI3SR1
424 //0x00C5 SCI3SR2
425 //0x00C6 SCI3DRH
426 //0x00C7 SCI3DRL
427 
428 
429 /* SCI0 debug/comms/datalogging TODO this is our primary serial interface for flash loading, setup serial comms software to communicate with MTX or similar for testing. */
430 #define SCI0_BASE 0x00C8
431 
432 #define SCI0BD DVUSP(SCI0_BASE + 0x0) /* #define SCI0BDH DVUCP(0x00C8), #define SCI0BDL DVUCP(0x00C9) (IR and baud control) */
433 #define SCI0CR1 DVUCP(SCI0_BASE + 0x2) /* Control reg 1 */
434 
435 #define SCI0ASR1 DVUCP(SCI0_BASE + 0x0) /* Status reg 1a (rx flags) */
436 #define SCI0ACR1 DVUCP(SCI0_BASE + 0x1) /* Control reg 1a (rx conf) */
437 #define SCI0ACR2 DVUCP(SCI0_BASE + 0x2) /* Control reg 2a (rx conf) */
438 
439 #define SCI0CR2 DVUCP(SCI0_BASE + 0x3) /* Control reg 2 */
440 #define SCI0SR1 DVUCP(SCI0_BASE + 0x4) /* Status reg 1 (isr flags) */
441 #define SCI0SR2 DVUCP(SCI0_BASE + 0x5) /* Status reg 2 (config/control) */
442 #define SCI0DRH DVUCP(SCI0_BASE + 0x6) /* Data reg high (9th bit bit 7 receive bit 6 send) */
443 #define SCI0DRL DVUCP(SCI0_BASE + 0x7) /* Data reg low (read and write for receive and send respectively)*/
444 
445 
446 /* SCI1 debug/comms/datalogging TODO this is our secondary serial interface, setup serial comms software to communicate with MTX or similar for testing. */
447 //0x00D0 SCI1BDH
448 //0x00D1 SCI1BDL
449 //0x00D2 SCI1CR1
450 
451 //0x00D0 SCI1ASR1
452 //0x00D1 SCI1ACR1
453 //0x00D2 SCI1ACR2
454 
455 //0x00D3 SCI1CR2
456 //0x00D4 SCI1SR1
457 //0x00D5 SCI1SR2
458 //0x00D6 SCI1DRH
459 //0x00D7 SCI1DRL
460 
461 
462 /* SPI0 */
463 #define SPI0CR1 DVUCP(0x00D8)
464 #define SPI0CR2 DVUCP(0x00D9)
465 #define SPI0BR DVUCP(0x00DA)
466 #define SPI0SR DVUCP(0x00DB)
467 #define SPI0DR DVUCP(0x00DD)
468 
469 
470 /* IIC0 */
471 //0x00E0 IBAD
472 //0x00E1 IBFD
473 //0x00E2 IBCR
474 //0x00E3 IBSR
475 //0x00E4 IBDR
476 
477 
478 /* SPI1 */
479 //0x00F0 SPI1CR1
480 //0x00F1 SPI1CR2
481 //0x00F2 SPI1BR
482 //0x00F3 SPI1SR
483 //0x00F5 SPI1DR
484 
485 
486 /* SPI2 */
487 //0x00F8 SPI2CR1
488 //0x00F9 SPI2CR2
489 //0x00FA SPI2BR
490 //0x00FB SPI2SR
491 //0x00FD SPI2DR
492 
493 
494 /* Flash Control Registers */
495 #define FCLKDIV DVUCP(0x0100) /* Flash Clock Divider Register R/W */
496 #define FSEC DVUCP(0x0101) /* Flash Security Register R */
497 #define FCNFG DVUCP(0x0103) /* Flash Configuration Register R/W */
498 #define FPROT DVUCP(0x0104) /* Flash Protection Register R/W */
499 #define FSTAT DVUCP(0x0105) /* Flash Status Register R/W */
500 #define FCMD DVUCP(0x0106) /* Flash Command Register R/W */
501 #define FCTL DVUCP(0x0107) /* Flash Control Register R */
502 
503 #define FADDR DVUSP(0x0108) /* Flash Low Address Register R (0x0108 FADDRHI, 0x0109 FADDRLO) */
504 #define FDATA DVUSP(0x010A) /* Flash High Data Register R (0x010A FDATAHI, 0x010B FDATALO) */
505 
506 
507 /* EEPROM Control Registers TODO learn how to use these to write data to the eeprom through serial comms. */
508 //0x0110 ECLKDIV
509 //0x0113 ECNFG
510 //0x0114 EPROT
511 //0x0115 ESTAT
512 //0x0116 ECMD
513 //0x0118 EADDRHI
514 //0x0119 EADDRLO
515 //0x011A EDATAHI
516 //0x011B EDATALO
517 
518 
519 //// IM
520 #define IVBR DVUCP(0x0121) /* Interrupt vector table base location first byte (second is always 0x00) */
521 #define INT_XGPRIO DVUCP(0x0126)
522 #define INT_CFADDR DVUCP(0x0127)
523 #define INT_CFDATA0 DVUCP(0x0128)
524 #define INT_CFDATA_ARR AVUCP(0x0128)
525 #define INT_CFDATA1 DVUCP(0x0129)
526 #define INT_CFDATA2 DVUCP(0x012A)
527 #define INT_CFDATA3 DVUCP(0x012B)
528 #define INT_CFDATA4 DVUCP(0x012C)
529 #define INT_CFDATA5 DVUCP(0x012D)
530 #define INT_CFDATA6 DVUCP(0x012E)
531 #define INT_CFDATA7 DVUCP(0x012F)
532 
533 
534 /* SCI4 */
535 //0x0130 SCI4BDH
536 //0x0130 SCI4ASR1
537 //0x0131 SCI4BDL
538 //0x0131 SCI4ACR1
539 //0x0132 SCI4CR1
540 //0x0132 SCI4ACR2
541 //0x0133 SCI4CR2
542 //0x0134 SCI4SR1
543 //0x0135 SCI4SR2
544 //0x0136 SCI4DRH
545 //0x0137 SCI4DRL
546 
547 
548 /* SCI5 */
549 //0x0138 SCI5BDH
550 //0x0138 SCI5ASR1
551 //0x0139 SCI5BDL
552 //0x0139 SCI5ACR1
553 //0x013A SCI5CR1
554 //0x013A SCI5ACR2
555 //0x013B SCI5CR2
556 //0x013C SCI5SR1
557 //0x013D SCI5SR2
558 //0x013E SCI5DRH
559 //0x013F SCI5DRL
560 
561 
562 /* CAN0 don't want this for now, leave it disabled too. CAN0CTL1 bit 7 should be set to zero to disable this. */
563 //0x0140 CAN0CTL0
564 #define CAN0CTL1 DVUCP(0x0141)
565 //0x0142 CAN0BTR0
566 //0x0143 CAN0BTR1
567 //0x0144 CAN0RFLG
568 //0x0145 CAN0RIER
569 //0x0146 CAN0TFLG
570 //0x0147 CAN0TIER
571 //0x0148 CAN0TARQ
572 //0x0149 CAN0TAAK
573 //0x014A CAN0TBSEL
574 //0x014B CAN0IDAC
575 //0x014D CAN0MISC
576 //0x014E CAN0RXERR
577 //0x014F CAN0TXERR
578 //0x0150 – 0x0153 : CAN0IDAR0 – CAN0IDAR3
579 //0x0154 – 0x0157 : CAN0IDMR0 – CAN0IDMR3
580 //0x0158 – 0x015B : CAN0IDAR4 – CAN0IDAR7
581 //0x015C – 0x015F : CAN0IDMR4 – CAN0IDMR7
582 //0x0160 – 0x016F : CAN0RXFG
583 //0x0170 – 0x017F : CAN0TXFG
584 
585 
586 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
587 //this block applies to all can maps!!!
588 //
589 //0xXXX0
590 //Extended ID
591 //Standard ID
592 //CANxRIDR0
593 //0xXXX1
594 //Extended ID
595 //Standard ID
596 //CANxRIDR1
597 //0xXXX2
598 //Extended ID
599 //Standard ID
600 //CANxRIDR2
601 //0xXXX3
602 //Extended ID
603 //Standard ID
604 //CANxRIDR3
605 //
606 //0xXXX4–
607 //0xXXXB
608 //CANxRDSR0–
609 //CANxRDSR7
610 //0xXXXC CANRxDLR
611 //0xXXXD Reserved
612 //0xXXXE CANxRTSRH
613 //0xXXXF CANxRTSRL
614 //0xXX10
615 //Extended ID
616 //CANxTIDR0
617 //Standard ID
618 //
619 //0xXX0x
620 //XX10
621 //Extended ID
622 //CANxTIDR1
623 //Standard ID
624 //0xXX12
625 //Extended ID
626 //CANxTIDR2
627 //Standard ID
628 //0xXX13
629 //Extended ID
630 //CANxTIDR3
631 //Standard ID
632 //
633 //0xXX14–
634 //0xXX1B
635 //CANxTDSR0–
636 //CANxTDSR7
637 //
638 //0xXX1C CANxTDLR
639 //0xXX1D CANxTTBPR
640 //0xXX1E CANxTTSRH
641 //0xXX1F CANxTTSRL
642 
643 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&77
644 
645 
646 /* CAN1 don't want this for now, leave it disabled too. CAN1CTL1 bit 7 should be set to zero to disable this. */
647 //0x0180 CAN1CTL0
648 #define CAN1CTL1 DVUCP(0x0181)
649 //0x0182 CAN1BTR0
650 //0x0183 CAN1BTR1
651 //0x0184 CAN1RFLG
652 //0x0185 CAN1RIER
653 //0x0186 CAN1TFLG
654 //0x0187 CAN1TIER
655 //0x0188 CAN1TARQ
656 //0x0189 CAN1TAAK
657 //0x018A CAN1TBSEL
658 //0x018B CAN1IDAC
659 //0x018D CAN1MISC
660 //0x018E CAN1RXERR
661 //0x018F CAN1TXERR
662 //0x0190 CAN1IDAR0
663 //0x0191 CAN1IDAR1
664 //0x0192 CAN1IDAR2
665 //0x0193 CAN1IDAR3
666 //0x0194 CAN1IDMR0
667 //0x0195 CAN1IDMR1
668 //0x0196 CAN1IDMR2
669 //0x0197 CAN1IDMR3
670 //0x0198 CAN1IDAR4
671 //0x0199 CAN1IDAR5
672 //0x019A CAN1IDAR6
673 //0x019B CAN1IDAR7
674 //0x019C CAN1IDMR4
675 //0x019D CAN1IDMR5
676 //0x019E CAN1IDMR6
677 //0x019F CAN1IDMR7
678 //0x01A0 – 0x01AF : CAN1RXFG
679 //0x01B0 – 0x01BF : CAN1TXFG
680 
681 
682 /* CAN2 CAN2CTL1 bit 7 should be set to zero to disable this. */
683 //0x01C0 CAN2CTL0
684 //0x01C1 CAN2CTL1
685 //0x01C2 CAN2BTR0
686 //0x01C3 CAN2BTR1
687 //0x01C4 CAN2RFLG
688 //0x01C5 CAN2RIER
689 //0x01C6 CAN2TFLG
690 //0x01C7 CAN2TIER
691 //0x01C8 CAN2TARQ
692 //0x01C9 CAN2TAAK
693 //0x01CA CAN2TBSEL
694 //0x01CB CAN2IDAC
695 //0x01CD CAN2MISC
696 //0x01CE CAN2RXERR
697 //0x01CF CAN2TXERR
698 //0x01D0 CAN2IDAR0
699 //0x01D1 CAN2IDAR1
700 //0x01D2 CAN2IDAR2
701 //0x01D3 CAN2IDAR3
702 //0x01D4 CAN2IDMR0
703 //0x01D5 CAN2IDMR1
704 //0x01D6 CAN2IDMR2
705 //0x01D7 CAN2IDMR3
706 //0x01D8 CAN2IDAR4
707 //0x01D9 CAN2IDAR5
708 //0x01DA CAN2IDAR6
709 //0x01DB CAN2IDAR7
710 //0x01DC CAN2IDMR4
711 //0x01DD CAN2IDMR5
712 //0x01DE CAN2IDMR6
713 //0x01DF CAN2IDMR7
714 //0x01E0 – 0x01EF : CAN2RXFG
715 //0x01F0 – 0x01FF : CAN2TXFG
716 
717 
718 /* CAN3 CAN3CTL1 bit 7 should be set to zero to disable this. */
719 //0x0200 CAN3CTL0
720 #define CAN3CTL1 DVUCP(0x0201)
721 //0x0202 CAN3BTR0
722 //0x0203 CAN3BTR1
723 //0x0204 CAN3RFLG
724 //0x0205 CAN3RIER
725 //0x0206 CAN3TFLG
726 //0x0207 CAN3TIER
727 //0x0208 CAN3TARQ
728 //0x0209 CAN3TAAK
729 //0x020A CAN3TBSEL
730 //0x020B CAN3IDAC
731 //0x020E CAN3RXERR
732 //0x020F CAN3TXERR
733 //0x0210 CAN3IDAR0
734 //0x0211 CAN3IDAR1
735 //0x0212 CAN3IDAR2
736 //0x0213 CAN3IDAR3
737 //0x0214 CAN3IDMR0
738 //0x0215 CAN3IDMR1
739 //0x0216 CAN3IDMR2
740 //0x0217 CAN3IDMR3
741 //0x0218 CAN3IDAR4
742 //0x0219 CAN3IDAR5
743 //0x021A CAN3IDAR6
744 //0x021B CAN3IDAR7
745 //0x021C CAN3IDMR4
746 //0x021D CAN3IDMR5
747 //0x021E CAN3IDMR6
748 //0x021F CAN3IDMR7
749 //0x0220 – 0x022F : CAN3RXFG
750 //0x0230 – 0x023F : CAN3TXFG
751 
752 
753 /* CAN4 CAN4CTL1 bit 7 should be set to zero to disable this. */
754 //0x0280 CAN4CTL0
755 #define CAN4CTL1 DVUCP(0x0281)
756 //0x0282 CAN4BTR0
757 //0x0283 CAN4BTR1
758 //0x0284 CAN4RFLG
759 //0x0285 CAN4RIER
760 //0x0286 CAN4TFLG
761 //0x0287 CAN4TIER
762 //0x0288 CAN4TARQ
763 //0x0289 CAN4TAAK
764 //0x028A CAN4TBSEL
765 //0x028B CAN4IDAC
766 //0x028D CAN4MISC
767 //0x028E CAN4RXERR
768 //0x028F CAN4TXERR
769 //0x0290 CAN4IDAR0
770 //0x0291 CAN4IDAR1
771 //0x0292 CAN4IDAR2
772 //0x0293 CAN4IDAR3
773 //0x0294 CAN4IDMR0
774 //0x0295 CAN4IDMR1
775 //0x0296 CAN4IDMR2
776 //0x0297 CAN4IDMR3
777 //0x0298 CAN4IDAR4
778 //0x0299 CAN4IDAR5
779 //0x029A CAN4IDAR6
780 //0x029B CAN4IDAR7
781 //0x029C CAN4IDMR4
782 //0x029D CAN4IDMR5
783 //0x029E CAN4IDMR6
784 //0x029F CAN4IDMR7
785 //0x02A0 – 0x02AF : CAN4RXFG
786 //0x02B0 – 0x02BF : CAN4TXFG
787 
788 
789 /* ATD0 TODO configure this as ATD inputs and try them out to control rate of flashing of leds etc, or even, which LED's are flashing etc */
790 #define ATD0CTL0 DVUCP(0x02C0) /* 0 - 2 define which ADC channel to wrap on when doing multiple channels */
791 #define ATD0CTL1 DVUCP(0x02C1) /* External trigger select when enabled in other control register */
792 #define ATD0CTL2 DVUCP(0x02C2) /* bit 7 turns the ADC block on. */
793 #define ATD0CTL3 DVUCP(0x02C3) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */
794 #define ATD0CTL4 DVUCP(0x02C4) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */
795 #define ATD0CTL5 DVUCP(0x02C5) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */
796 //0x02C6 ATD0STAT0
797 //0x02CB ATD0STAT1
798 #define ATD0DIEN DVUCP(0x02CD) /* Digital input enable */
799 //0x02CF ATD0PTAD0 digital use only
800 #define ATD0_BASE 0x02D0 /* Maybe use this with a loop to sample them in a compact way. */
801 #define ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */
802 #define ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */
803 #define ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */
804 #define ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */
805 #define ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */
806 #define ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */
807 #define ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */
808 #define ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */
809 
810 
811 /* VREG unit, Low Voltage Interrupt and Autonomous Periodical Interrupt */
812 #define VREGCTRL DVUCP(0x02F1) /* VReg Control Register */
813 #define VREGAPICL DVUCP(0x02F2) /* Autonomous Periodical Interrupt Control Register */
814 #define VREGAPITR DVUCP(0x02F3) /* Autonomous Periodical Interrupt Trimming Register */
815 #define VREGAPIR DVUSP(0x02F4) /* Autonomous Periodical Interrupt Rate High and Low Registers (VREGAPIRH DVUCP(0x02F4), VREGAPIRL DVUCP(0x02F5)) */
816 
817 
818 #define PWME DVUCP(0x0300) /* PWM enable register */
819 #define PWMPOL DVUCP(0x0301) /* PWM polarity register */
820 #define PWMCLK DVUCP(0x0302) /* PWM clock choice register */
821 #define PWMPRCLK DVUCP(0x0303) /* PWM Clock prescalers (bits 0,1,2 and bits 4,5,6 control 4 pins each) */
822 #define PWMCAE DVUCP(0x0304) /* PWM Center Align Enable Register */
823 #define PWMCTL DVUCP(0x0305) /* PWM Concatenate, stop, wait, freeze register */
824 #define PWMSCLA DVUCP(0x0308) /* PWM Scale A register */
825 #define PWMSCLB DVUCP(0x0309) /* PWM Scale B register */
826 #define PWMCNT0 DVUCP(0x030C) /* PWM 8 bit counter */
827 #define PWMCNT1 DVUCP(0x030D) /* */
828 #define PWMCNT2 DVUCP(0x030E) /* */
829 #define PWMCNT3 DVUCP(0x030F) /* */
830 #define PWMCNT4 DVUCP(0x0310) /* */
831 #define PWMCNT5 DVUCP(0x0311) /* */
832 #define PWMCNT6 DVUCP(0x0312) /* */
833 #define PWMCNT7 DVUCP(0x0313) /* PWM 8 bit counter */
834 #define PWMPER0 DVUCP(0x0314) /* PWM period value */
835 #define PWMPER1 DVUCP(0x0315) /* */
836 #define PWMPER2 DVUCP(0x0316) /* */
837 #define PWMPER3 DVUCP(0x0317) /* */
838 #define PWMPER4 DVUCP(0x0318) /* */
839 #define PWMPER5 DVUCP(0x0319) /* */
840 #define PWMPER6 DVUCP(0x031A) /* */
841 #define PWMPER7 DVUCP(0x031B) /* PWM period value */
842 #define PWMDTY0 DVUCP(0x031C) /* PWM duty cycle value */
843 #define PWMDTY1 DVUCP(0x031D) /* */
844 #define PWMDTY2 DVUCP(0x031E) /* */
845 #define PWMDTY3 DVUCP(0x031F) /* */
846 #define PWMDTY4 DVUCP(0x0320) /* */
847 #define PWMDTY5 DVUCP(0x0321) /* */
848 #define PWMDTY6 DVUCP(0x0322) /* */
849 #define PWMDTY7 DVUCP(0x0323) /* PWM duty cycle value */
850 #define PWMSDN DVUCP(0x0324) /* PWM shutdown behaviour register */
851 
852 
853 /* Periodic Interupt Timer with down counter */
854 #define PITCFLMT DVUCP(0x0340) /* PIT Control and Force Load Micro Timer Register, high bit enables, low 2 bits force load micro timers */
855 #define PITFLT DVUCP(0x0341) /* PIT Force Load Timer Register, low 4 bits force load timers */
856 #define PITCE DVUCP(0x0342) /* PIT Channel Enable Register, low 4 bits let the channel count */
857 #define PITMUX DVUCP(0x0343) /* PIT Multiplex Register, low 4 bits set which micro time base is used */
858 #define PITINTE DVUCP(0x0344) /* PIT Interrupt Enable Register, low four bits control the ISRs */
859 #define PITTF DVUCP(0x0345) /* PIT Time-Out Flag Register, low 4 bits set when each counter reaches 0 */
860 #define PITMTLD0 DVUCP(0x0346) /* PIT Micro Timer Load Register 0, time to start counting from when reaching zero */
861 #define PITMTLD1 DVUCP(0x0347) /* PIT Micro Timer Load Register 1, time to start counting from when reaching zero */
862 #define PITLD0 DVUSP(0x0348) /* PIT Load Register 0, time to start counting from when reaching zero (0x0348 PITLD0 (hi), 0x0349 PITLD0 (lo)) */
863 #define PITLD1 DVUSP(0x034C) /* PIT Load Register 1, time to start counting from when reaching zero (0x034C PITLD1 (hi), 0x034D PITLD1 (lo)) */
864 #define PITLD2 DVUSP(0x0350) /* PIT Load Register 2, time to start counting from when reaching zero (0x0350 PITLD2 (hi), 0x0351 PITLD2 (lo)) */
865 #define PITLD3 DVUSP(0x0354) /* PIT Load Register 3, time to start counting from when reaching zero (0x0354 PITLD3 (hi), 0x0355 PITLD3 (lo)) */
866 #define PITCNT0 DVUSP(0x034A) /* PIT Count Register 0, current value of down counter (0x034A PITCNT0 (hi), 0x034B PITCNT0 (lo)) */
867 #define PITCNT1 DVUSP(0x034E) /* PIT Count Register 1, current value of down counter (0x034E PITCNT1 (hi), 0x034F PITCNT1 (lo)) */
868 #define PITCNT2 DVUSP(0x0352) /* PIT Count Register 2, current value of down counter (0x0352 PITCNT2 (hi), 0x0353 PITCNT2 (lo)) */
869 #define PITCNT3 DVUSP(0x0356) /* PIT Count Register 3, current value of down counter (0x0356 PITCNT3 (hi), 0x0357 PITCNT3 (lo)) */
870 
871 
872 #define XGMCTL DVUSP(0x0380)
873 #define XGMCTLHI DVUCP(0x0380)
874 #define XGMCTLLO DVUCP(0x0381)
875 #define XGCHID DVUCP(0x0382)
876 // unused on xdp512 #define XGVBR DVUCP(0x0384)
877 // unused on xdp512 #define XGVBR DVUCP(0x0385)
878 #define XGVBR DVUSP(0x0386) /* This is all that is used on the xdp512! 16 bit (0x0386 DVUCP (hi), 0x0387 DVUCP (lo)) */
879 #define XGIF_0 DVUCP(0x0388)
880 #define XGIF_1 DVUCP(0x0389)
881 #define XGIF_2 DVUCP(0x038A)
882 #define XGIF_3 DVUCP(0x038B) /* WRONG value 0x023B stated in the manual as being both xgate and can3!!!!! should be 0x038B i believe!!!!! */
883 #define XGIF_4 DVUCP(0x038C) /* WRONG value 0x023C stated in the manual as being both xgate and can3!!!!! should be 0x038C i believe!!!!! */
884 #define XGIF_5 DVUCP(0x038D)
885 #define XGIF_6 DVUCP(0x038E)
886 #define XGIF_7 DVUCP(0x038F)
887 #define XGIF_8 DVUCP(0x0390)
888 #define XGIF_9 DVUCP(0x0391)
889 #define XGIF_A DVUCP(0x0392)
890 #define XGIF_B DVUCP(0x0393)
891 #define XGIF_C DVUCP(0x0394)
892 #define XGIF_D DVUCP(0x0395)
893 #define XGIF_E DVUCP(0x0396)
894 #define XGIF_F DVUCP(0x0397)
895 #define XGSWT DVUSP(0x0398)
896 //#define DVUCP(0x0399 XGSWT (lo)
897 #define XGSEM DVUSP(0x039A)
898 //#define DVUCP(0x039B XGSEM (lo)
899 #define XGCCR DVUCP(0x039D)
900 #define XGPC DVUSP(0x039E)
901 //#define DVUCP(0x039F XGPC (lo)
902 #define XGR1 DVUSP(0x03A2)
903 //#define DVUCP(0x03A3 XGR1 (lo)
904 #define XGR2 DVUSP(0x03A4)
905 //#define DVUCP(0x03A5 XGR2 (lo)
906 #define XGR3 DVUSP(0x03A6)
907 //#define DVUCP(0x03A7 XGR3 (lo)
908 #define XGR4 DVUSP(0x03A8)
909 //#define DVUCP(0x03A9 XGR4 (lo)
910 #define XGR5 DVUSP(0x03AA)
911 //#define DVUCP(0x03AB XGR5 (lo)
912 #define XGR6 DVUSP(0x03AC)
913 //#define DVUCP(0x03AD XGR6 (lo)
914 #define XGR7 DVUSP(0x03AE)
915 //#define DVUCP(0x03AF XGR7 (lo)
916 
917 
918 //// DBG
919 //0x0020 DBGC1 DVUCP() /*
920 //0x0021 DBGSR DVUCP() /*
921 //0x0022 DBGTCR DVUCP() /*
922 //0x0023 DBGC2 DVUCP() /*
923 //0x0024 DBGTBH DVUCP() /*
924 //0x0025 DBGTBL DVUCP() /*
925 //0x0026 DBGCNT DVUCP() /*
926 //0x0027 DBGSCRX DVUCP() /*
927 //COMPA 0x0028 DVUCP() /*
928 //COMPC 0x0028 DVUCP() /*
929 //DBGXCTL 0x0028 DVUCP() /*
930 //COMPB 0x0028 DVUCP() /*
931 //COMPD 0x0028 DVUCP() /*
932 //0x0029 DBGXAH DVUCP() /*
933 //0x002A DBGXAM DVUCP() /*
934 //0x002B DBGXAL DVUCP() /*
935 //0x002C DBGXDH DVUCP() /*
936 //0x002D DBGXDL DVUCP() /*
937 //0x002E DBGXDHM DVUCP() /*
938 //0x002F DBGXDLM DVUCP() /*
939 
940 
941 /* All reserved registers/blocks are listed here for reference */
942 
943 /* 0x003E CTCTL COP test register */
944 /* 0x006D TIMTST Timer test register */
945 /* 0x0102 FTSTMOD Flash test register */
946 /* 0x02C8 ATD0TEST0 ADC test register */
947 /* 0x02C9 ATD0TEST1 ADC test register */
948 /* 0x02F0 VREGHTCL VReg test register */
949 /* 0x0306 PWMTST PWM test register */
950 /* 0x0307 PWMPRSC PWM test register 2 */
951 /* 0x030A PWMSCNTA PWM test register 3 */
952 /* 0x030B PWMSCNTB PWM test register 4 */
953 
954 
955 /* 0x001D Reserved */
956 /* 0x001F Reserved */
957 /* 0x0012 Reserved */
958 /* 0x0014 - 0x0015 : Reserved */
959 /* 0x0018 - 0x0019 : Reserved */
960 /* 0x0031 Reserved */
961 /* 0x006C Reserved */
962 /* 0x00B5 - 0x00B7 : Reserved */
963 /* 0x0087 Reserved */
964 /* 0x00DC Reserved */
965 /* 0x00DE - 0x00DF : Reserved */
966 /* 0x00E5 - 0x00EF : Reserved */
967 /* 0x00F4 Reserved */
968 /* 0x00F6 Reserved */
969 /* 0x00F7 Reserved */
970 /* 0x00FC Reserved */
971 /* 0x00FE - 0x00FF : Reserved */
972 /* 0x010C - 0x010F : Reserved */
973 /* 0x0111 Reserved */
974 /* 0x0112 Reserved */
975 /* 0x0117 Reserved */
976 /* 0x0120 Reserved */
977 /* 0x0122 - 0x0125 : Reserved */
978 /* 0x014C Reserved */
979 /* 0x018C Reserved */
980 /* 0x01CC Reserved */
981 /* 0x020C - 0x020D : Reserved */
982 /* 0x0246 - 0x0247 : Reserved */
983 /* 0x024F Reserved */
984 /* 0x0270 Reserved */
985 /* 0x0272 Reserved */
986 /* 0x0274 Reserved */
987 /* 0x0276 Reserved */
988 /* 0x028C Reserved */
989 /* 0x02C7 Reserved */
990 /* 0x02CA Reserved */
991 /* 0x02CC Reserved */
992 /* 0x02CE Reserved */
993 /* 0x02E0 – 0x02EF : Reserved */
994 /* 0x02F6 – 0x02FF : Reserved */
995 /* 0x0325 – 0x033F : Reserved */
996 /* 0x0358 – 0x037F : Reserved */
997 /* 0x0383 Reserved */
998 /* 0x039C Reserved */
999 /* 0x03A0 Reserved */
1000 /* 0x03A1 Reserved */
1001 /* 0x03B0 – 0x07FF : Reserved */
1002 
1003 
1004 /* Clear any accidental use of Reserved from typing mistakes. */
1005 #ifdef Reserved
1006  #error "We have accidentally defined reserved as Reserved in here, find it and fix it."
1007 #endif
1008 
1009 
1010 #else
1011  /* let us know if we are being untidy with headers */
1012  #warning "Header file 9S12XDP512_H seen before, sort it out!"
1013 /* end of the wrapper ifdef from the very top */
1014 #endif