init.h File Reference

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Macros
#define	EXTERN   extern
#define	PLLSELOFF   0x7F /* Mask for switching to base external OSCCLK clock 0b_0111_1111 */
#define	PLLOFF   0xBF /* Mask for turning the PLLON bit to ZERO 0b_1011_1111, IE, turning PLL off */
#define	PLLDIVISOR   0x03 /* Input crystal frequency is divided by this number */
#define	PLLMULTIPLIER   0x09 /* The result of the above is multiplied by this number to give the bus frequency */
#define	PRDIV8   0x40 /* Mask for flash module to divide the oscillator clock by 8 */

Functions
void	init (void) FPAGE_FE
	The main top level init.
void	enablePLL (void) FPAGE_FE
	Switch to using PLL.

Detailed Description

Definition in file init.h.

Macro Definition Documentation

#define EXTERN   extern

Definition at line 79 of file init.h.

#define PLLSELOFF   0x7F /* Mask for switching to base external OSCCLK clock 0b_0111_1111 */

Definition at line 95 of file init.h.

Referenced by initPLL().

#define PLLOFF   0xBF /* Mask for turning the PLLON bit to ZERO 0b_1011_1111, IE, turning PLL off */

Definition at line 96 of file init.h.

Referenced by initPLL().

#define PLLDIVISOR   0x03 /* Input crystal frequency is divided by this number */

Definition at line 97 of file init.h.

Referenced by initPLL().

#define PLLMULTIPLIER   0x09 /* The result of the above is multiplied by this number to give the bus frequency */

Definition at line 98 of file init.h.

Referenced by initPLL().

#define PRDIV8   0x40 /* Mask for flash module to divide the oscillator clock by 8 */

Definition at line 101 of file init.h.

Function Documentation

void init

(

void

)

The main top level init.

The main init function to be called from main.c before entering the main loop. This function is simply a delegator to the finer grained special purpose init functions.

Definition at line 61 of file init.c.

References ATOMIC_END, ATOMIC_START, initADC(), initAllPagedRAM(), initConfiguration(), initECTTimer(), initFlash(), initGPIO(), initInterrupts(), initPLL(), initPWM(), initSCIStuff(), and initVariables().

Referenced by decodePacketAndRespond(), and main().

           {
    ATOMIC_START();         /* Disable ALL interrupts while we configure the board ready for use */
    initPLL();              /* Set up the PLL and use it */
    initGPIO();
    initPWM();
    initADC();
    initAllPagedRAM();      /* Copy table and config blocks of data from flash to the paged RAM blocks for fast data lookup */
    initVariables();        /* Initialise the rest of the running variables etc */
    initFlash();            /* TODO, finalise this */
    initECTTimer();         /* TODO move this to inside config in an organised way. Set up the timer module and its various aspects */
//  initPITTimer();         /* TODO ditto... */
    initSCIStuff();         /* Setup the sci module(s) that we will use. */
    initConfiguration();    /* TODO Set user/feature/config up here! */
#ifdef XGATE
    initXgate();            /* Fred is a legend, for good reason as of now */
#endif
    initInterrupts();       /* still last, reset timers, enable interrupts here TODO move this to inside config in an organised way. Set up the rest of the individual interrupts */
    ATOMIC_END();           /* Re-enable any configured interrupts */
}

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void enablePLL

(

void

)

Switch to using PLL.

Switch to using PLL for clock (40MHz bus speed). Interrupt is enabled elsewhere.

Note: Requires busy wait loop, only for init and emergency use.

Todo:

Should be limited, and have break out with error code and fall back mechanism.

Definition at line 108 of file init.c.

References CLKSEL, CRGFLG, PLLLOCK, and PLLSEL.

Referenced by initPLL(), and SelfClockISR().

                {
    while (!(CRGFLG & PLLLOCK)){
        /* Do nothing while we wait till the PLL loop locks onto the target frequency. */
        /* Target frequency is given by (2 * (crystal frequency / (REFDV + 1)) * (SYNR + 1)) */
        /* Bus frequency is half PLL frequency and given by ((crystal frequency / (REFDV + 1)) * (SYNR + 1)) */
    }

    CLKSEL = PLLSEL; /* Switches to PLL clock for internal bus frequency        */
    /* from MC9S12XDP512V2.pdf Section 2.4.1.1.2 page 101 Third paragraph       */
    /* "This takes a MAXIMUM of 4 OSCCLK clock cylces PLUS 4 PLL clock cycles"  */
    /* "During this time ALL clocks freeze, and CPU activity ceases"            */
    /* Therefore there is no point waiting for this to occur, we already are... */
}

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